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2001 Microchip Technology Inc.

DS39026C-page 133

PIC18CXX2

14.4.2

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the START condition usually deter-

mines which device will be the slave addressed by the

master. The exception is the general call address which

can address all devices. When this address is used, all

devices should, in theory, respond with an acknowl-

edge.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all 0’s with R/W = 0.

The general call address is recognized when the Gen-

eral Call Enable bit (GCEN) is enabled (SSPCON2<7>

is set). Following a START bit detect, 8-bits are shifted

into the SSPSR and the address is compared against

the SSPADD. It is also compared to the general call

address and fixed in hardware.

If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit), and on the falling edge of the ninth bit (ACK bit),

the SSPIF interrupt flag bit is set.

When the interrupt is serviced, the source for the inter-

rupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match, and the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-bit address mode, then the second

half of the address is not necessary, the UA bit will not

be set, and the slave will begin receiving data after the

Acknowledge (Figure 14-12).

FIGURE 14-12:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

14.4.3

MASTER MODE

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a RESET or when the MSSP module is

disabled. Control of the I2C bus may be taken when the

P bit is set, or the bus is idle, with both the S and P bits

clear.

In Master mode, the SCL and SDA lines are manipu-

lated by the MSSP hardware.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP interrupt, if enabled):

START condition

STOP condition

Data transfer byte transmitted/received

Acknowledge Transmit

Repeated START

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

Cleared in software

SSPBUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

GCEN (SSPCON2<7>)

Receiving Data

ACK

after ACK, set interrupt

’0’

’1’

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